Reconfigurable Hardware & It's Software Interface
An Annotated Bibliography
By: Steven Stanek & Robert El-Soudani

Paper: John R. Hauser and John Wawrzyneck, "Garp: A MIPS Processor with a Reconfigurable Coprocessor", Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97, April 16-18, 1997) pp. 24-33.
Description: This paper describes GARP, a specific implementation of an integrated FPGA & MIPS II CPU. The paper discusses hardware design, programming and testing details but deals only with simulated results; no hardware was built at the time of publication.

Paper: John R. Hauser, "The GARP Architecture"
Description: A more thorough specification of the GARP Architecture than in "Garp: A MIPS Processor with a Reconfigurable Coprocessor".

Paper: Timothy John Callahan, "Automatic Compilation of C for Hybrid Reconfigurable Architectures", PhD Thesis, University of California, Berkeley, 2002
Description: This paper deals specifically with compiling C to the GARP architecture but techniques described many be applied to more general languages and architectures.

Paper: Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy, John Wawrzynek, and André DeHon, "Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial", extended version of the paper appearing in Conference on Field Programmable Logic and Applications, August 28--30, 2000
Description: Deals with a "stream based computer model which virtualizes reconfigurable computing resources (compute, storage, and communication) by dividing a computation up into fixed-size ``pages'' and time-multiplexing the virtual pages on available physical hardware".

Paper: Andre Hon, "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century", Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1994, pp 31-39
Description: Discusses trends leading toward FPGA integration on processors, limitations of current schemes and the possible applications that could benefit from integrated programmable logic.

Paper: Micheal J Wirthlin and Brad L. Hutchings, "A dynamic instruction set computer", Symposium on FPGAs for Custom Computing Machines, April 1995, pp 99-107
Description: Discusses the architecture and ramifications of treating instructions as "removable modules" which can be loaded when need into a FPGA and unloaded when not in use. In effect, the FPGA is treated as a cache for the most needed instructions, paging them in and out as needed.

Paper: J. Davidson, "FPGA implementation of a reconfigurable microprocessor", Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, pages 3.2.1-3.2.4, 1993.
Description:  Briefly discusses the implementation of an entire microprocessor in an FPGA with the belief that the it can be reconfigured to application specific tasks.


Paper: A. Wolfe and J.P. Shen. "Flexible processors: a promising application specific processor design approach". Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - Micro '21 p 30-39.

Paper: David Andrews, Douglas Niehaus, et al. "Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link", IEEE Micro Vol 24, No. 4, p 42-53.
Description: Discusses programming techniques for FPGA-CPU hybrids such as languages used, multithreading and operating system design including time keeping, interrupt processing and mutual exclusion.

Paper: S. Baldacci, V. Zolesi et at. "SEU Tolerant Controls for a Space Application based on Dynamically Reconfigurable FPGA".  MAPLD 2003 Paper C2.

The papers in the section I believe are probably important and relevant, but I have been unable to find their full text.

Paper (Haven't been able to find): T. G. Rauscher and A. K. Agrawala, "Dynamic problem-oriented redefinition of computer architecture via microprogramming", IEEE Transactions on Computers, C-27(11):1006-1014, November 1978.


Book: John Hennessey and David Patterson, Computer Architecture A Quantitative Approach, 3rd edition, Morgan Kaufmann, 2003
Description: Hennessey and Patterson contains a large quantity of information on instruction level parallelism (ILP) techniques, metrics for evaluating performance and discussions of die space issues, all of which we intend to address in our project.

Paper: Micheal J. Flynn, "Very High Speed Computing Systems", Proceedings of IEEE, vol 54, no. 12, December 1966
Description: This classical paper introduces many of the common notions of multiple issue machines: SISD, SIMD, MIMD, MISD. We will constrast the notions of programmable logic devices to these various classic schemes.

Paper: R. Ramakrishna Rau and Joseph A. Fisher, "Instruction Level Parallel Processing: History, Overview & Perspective" (I couldn't find what it was originally published in, but it's in Readings in Computer Architecture)
Description: Gives a thorough overview of past and present instruction level parallelism designs and techniques.